Embodiments of the present invention relate generally to a semiconductor memory device and a method for generating a reference voltage for operating the same, and more particularly to a semiconductor memory device including a reference voltage generator setting up an internal reference voltage, and a method for generating a reference voltage for operating the semiconductor memory device.
Semiconductor memory devices such as Dynamic Random Access Memories (DRAMs) are being widely used in electronic devices. With broadening uses of miniaturized high-speed electronic devices, the efforts to highly integrate the semiconductor devices and to improve its operation speed continue.
Joint Electron Device Engineering Council (JEDEC) serving as a semiconductor standardization organization has standardized a wide Input/Output (I/O) scheme considering a parallel-interface Low Power Double Data Rate (LPDDR) and a die stack package as the next-generation DRAM scheme. Many semiconductor companies are making efforts to develop DRAMs having more improved functions based on JEJEC standard.
With rapid development of mobile devices, the next-generation DRAMs optimized for such mobile devices have been rapidly developed to have smaller sizes and lower power consumption. Specifically, various attempts, such as voltage scaling, structural improvement, new I/O signaling, and signal-integration improvement, have been made to achieve low power consumption as well as to compensate for power consumption due to a high-speed operation.